The present invention relates to a non-volatile memory semiconductor device and a method for manufacturing a non-volatile memory semiconductor device, and more particularly, to a non-volatile memory semiconductor device having a two-bits per cell not-and-gate (NAND) nitride trap memory and a method for manufacturing a non-volatile memory semiconductor device having a two-bits per cell NAND nitride trap memory.
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing such an NVM memory cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM) and Electrically Erasable Programmable Read-Only Memory (EEPROM). Typically, NVM can be programmed with data, read and/or erased, and the programmed data can be stored for a long period of time prior to being erased, even as long as ten years.
Nitride read only memory (NROM) is a type of EEPROM that uses charge-trapping for data storage. An NROM cell is typically composed of a metal-oxide-silicon field effect transistor (MOSFET) having an ONO (oxide-nitride-oxide) layer disposed between the gate and the source/drain of the semiconductor material. The nitride layer in the ONO layer is able to “trap” charge (electrons) when the device is “programmed.” Charge localization is the ability of the nitride material to store the charge without significant lateral movement of the charge throughout the nitride layer. NROM utilizes a relatively thick tunnel oxide layer, which typically negatively impacts the time it takes to erase a memory cell. NROM can be contrasted with conventional “floating gate” memory cells wherein the floating gate is conductive and the charge is spread laterally throughout the entire floating gate and charge is transferred through a tunnel oxide layer. Programming (i.e., charge injection) of the charge-trapping layer in NROM cells can be carried out by various hot carrier injection methods such as channel hot electron injection (CHE), source side injection (SSI) or channel initiated secondary electron (CHISEL) which all inject electrons into the nitride layer. Erasing is performed by applying a positive gate voltage, which permits hole tunneling through the ONO top dielectric layer from the gate. Erasing (i.e., charge removal) in NROM devices is typically carried out by band-to-band hot hole tunneling (BTBHHT). However, BTBHHT erasing causes many reliability issues with NROM devices and causes degradation of the NROM devices and charge loss after many program/erase cycles. Reading is carried out in a forward or reverse direction. Localized charge-trapping technology allows two separate bits per cell, thus resulting in a doubling of memory density. The NROM can be repeatedly programmed, read, erased and/or reprogrammed by known voltage application techniques.
NROM has attracted attention because of the two bits per cell operation and simple process flow for fabrication. However, NROM memory encounters fundamental limitations as the design is scaled down because of short channel effect and source/drain punch-through. A typical NROM memory is disclosed in U.S. Pat. No. 5,768,192 (Eitan '192), the contents of which is incorporated by reference herein. The source/drain of NROM is formed by Arsenic implantation into a P-well. The doping is heavy and the source/drain junction is deep in order to produce channel hot electron injection for programming and band to band hot hole for erasing. As result, even with virtual ground array architecture, the cell size of a NROM memory cell is about 8F2-10F2, where F is the feature size. The heavy and deep source/drain limits the scaling of the NROM cell. Further, the large hot electron programming current make it hard to parallel program on the order of kilobytes (kB) which limits the application for data flash.
Another common EEPROM is a metal-nitride-oxide-silicon (MNOS) memory cell. A typical MNOS cell includes a very thin layer of insulating material like silicon dioxide (SiO2) to separate a silicon nitride charge storage region from a gate and from a well region of the semiconductor device. MNOS devices are programmed by applying a positive voltage potential to the gate electrode while forcing the source, drain and well regions to a lower voltage potential. By applying a higher voltage to the gate, an electric field is created causing electrons in the well region and the rest of the semiconductor to tunnel through the oxide layer to the nitride layer. In order for the electrons to be able to tunnel through the oxide layer, the oxide layer must be relatively thin, e.g., 20-30 Angstroms (Å).
Yet another known EEPROM is a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell. FIG. 1 depicts a typical conventional SONOS device 110. The conventional SONOS device 110 includes a silicon substrate 111, a source 114, a drain 112, a well region 115 and a first oxide layer 120 on top of the well region 115. A nitride charge storage layer 124 is provided above the first oxide layer 120 and a second oxide layer 130 is provided above the nitride charge storage layer 124. A polysilicon (poly) gate 125 is disposed on top of the ONO stack 120, 124, 130. By providing the second oxide layer 130 on top of the nitride layer 124 there is an improvement in the ability to control where the charge is stored or “trapped” within the nitride layer 124 during programming operations. Additionally, the second oxide layer 124 prevents holes from entering from the overlying gate 125. A non-volatile memory cell that utilizes asymmetric charge trapping is disclosed in Eitan '192.
U.S. Pat. No. 6,011,725 (Eitan '725), the entire contents of which is incorporated by reference herein, provides a detailed comparison of several of the prior art NVMs including respective programming, erasing and reading techniques. The Eitan '725 patent also discloses a type of SONOS memory cell capable of storing two data bits by localized charge storage techniques.
To program a first bit of typical conventional SONOS devices 110, a program voltage is applied to the drain 112 and to the gate 125 while the source 114 is grounded. The program voltage cause a vertical and lateral electric field along the length of the channel 105 from the source 114 to the drain 112. The electric field causes electrons to be drawn from the source 114 to the drain 112, and as the electrons move along a length of the channel 105, the electrons gain energy to “jump” the potential barrier posed by the bottom oxide layer 120 into the nitride charge storage layer 124 where they are “trapped” or stored. The accelerated electrons that make the jump are referred to as hot electrons. Since the nitride charge storage layer 124 is not really conductive, the electrons cannot spread throughout the nitride charge storage layer 124, but instead remain trapped in a local region closest to the drain 112. Similarly, to program a second bit of typical conventional SONOS devices 110, a program voltage is applied to the source 114 and to the gate 125 while the drain 112 is grounded. The program voltage cause a vertical and lateral electric field along the length of the channel 105 from the drain 112 to the source 114. The electric field causes electrons to be drawn from the drain 112 to the source 114, and as the electrons move along a length of the channel 105, the electrons gain energy to “jump” the potential barrier posed by the bottom oxide layer 120 into the nitride charge storage layer 124 where they are “trapped” or stored. Since the nitride charge storage layer 124 is not really conductive, the electrons cannot spread throughout the nitride charge storage layer 124, but instead remain trapped in a local region closest to the source 114. In order to be able to erase the memory, the programming duration must be limited because as the programming voltages continue to be applied, the width of the charge trapping region becomes wider and therefore harder to erase.
NAND flash memory has become the main stream technology for data flash application due to its smaller cell size and faster program speed and serial access. However, floating gate type NAND flash memory encounters fundamental limitations as the design is scaled down below 70 nanometers (nm). Besides its poor endurance, the interference effect due to parasitic capacitance between the adjacent floating gates severely deteriorates the cell threshold voltage distribution. Notably, SONOS NAND flash memory is free of such technological limitations generating below the design rule of 70 nm. However, SONOS NAND flash memory generally has poor charge retention which prevents SONOS NAND flash memory from being applied in high density NAND flash memory.
It is desirable to provide a non-volatile memory semiconductor device having a two-bits per cell NAND nitride trap memory. It is also desirable to provide an NVM having data retention that is better than SONOS NAND memory.